Switching regulators have been and will continue to be extremely popular as a power control element due to their inherent high efficiency and small size. Many switching regulator topologies require a rectifying function that is most easily accomplished using a diode. The “buck” or “step down” regulator is an example of this. FIG. 1 illustrates an exemplary prior art buck regulator using a catch diode. This regulator topology can efficiently produce a lower output voltage from a higher input voltage. The circuit functions in two modes, one where the PMOS (P-type metal-oxide-semiconductor transistor) switch is closed and another where the PMOS switch is open. FIG. 2 illustrates an exemplary prior art buck regulator showing current flow when the PMOS switch is on, and FIG. 3 illustrates an exemplary prior art buck regulator showing current flow when the PMOS switch is off. When the PMOS switch is closed, current will ramp up linearly in the inductor, and when the switch is open, the current continues to flow through the inductor in the same direction. Since the current cannot flow through the open PMOS switch, it will pull current out of the diode causing the cathode to become negative with respect to the anode. The diode used in this application is known as a “catch” diode or sometimes as a “freewheeling” diode. The rectifying function provided by the diode is advantageous in many other switching power supply topologies as well, such as, but not limited to, boost converters, flyback converters and forward converters.
When the PMOS switch is closed the voltage across the inductor is (Vin−Vout), assuming an ideal PMOS device. Current ramps up in the inductor in a linear fashion controlled by the equation V=L(di/dt) where V is the voltage across the inductor, L is the inductance of the inductor in Henries and di/dt is the derivative of inductor current with respect to time. When the PMOS switch is open the voltage across the inductor is (−Vbe−Vout) where Vbe represents the forward drop of the catch diode (normally 0.4V to 0.7V). The slope of the inductor current with respect to time reverses because the polarity of the voltage across the inductor is now opposite to what it was previously. For certain operational modes, such as discontinuous operation, it is possible that the inductor current will ramp all the way down to zero. At that point the current starts to reverse its direction, which causes the catch diode to reverse bias and stop the current flow. This prevents the output capacitor from being discharged back into the ground node.
A problem with using the catch diode for buck controllers, and other switching controllers in general, is that the inherent voltage drop across the catch diode multiplied by the current through the diode wastefully dissipates a significant amount of power. This power dissipation can be unacceptable in certain applications. For buck converters with high Vin/Vout ratios the problem is more acute because the time the PMOS is on (i.e., PMOS duty cycle) becomes shorter; this means that current flows through the diode for a greater proportion of each cycle. If the current spends more of its time flowing through the diode, the current also spends more of its time dissipating power in the diode, which brings down the overall system efficiency.
In order to mitigate the diode power dissipation problem designers sometimes use schottky diodes for catch diodes in these applications. A schottky diode has an inherently lower forward voltage than a silicon diode, hence, for the same current, the power dissipation is lower. Another known solution is to replace the catch diode with an approximation of a “perfect diode”. FIG. 4 shows an exemplary I-V curve of a prior art perfect diode. FIG. 5 illustrates exemplary prior art implementations of perfect diodes. A perfect diode can be implemented with a comparator and a switching element (PMOS or NMOS). Real applications do not have access to perfect comparators and switches, however using real FETs (field effect transistors) and real comparators to approximate a perfect diode does provide significant efficiency benefits beyond those of silicon or shottky catch diodes. FIG. 6 shows exemplary prior art buck and boost converters using perfect diodes. The examples shown are simplified applications using a perfect diode for both a buck configuration and a boost configuration. The technique of using active switching to provide rectification in switching power supply circuits is sometimes known as “synchronous switching”.
Comparator offset voltages and finite response times do limit the usefulness of the perfect diode schemes. The drawbacks become more acute as switching frequencies increase because the time available to make an accurate comparison becomes shorter. The graphs in FIGS. 7 and 8 show that the inductor current has actually reversed slightly before the comparator can respond and turn off the synchronous switch. The non-zero inductor current left over in the inductor will cause increased ringing when both FETs are turned off. It also increases power dissipation since the left over energy in the inductor is not delivered to the load.
FIG. 7 shows idealized waveforms and circuitry of a prior art buck converter in discontinuous mode showing the effect of inductor current overshoot. The waveforms and circuitry for the buck converter are analogous to the boost converter waveforms shown in FIG. 8. Position “C” on the waveforms is a positive signal as the LX node attempts to drive above Vin but is constrained by the body diode of the PMOS device.
FIG. 8 shows idealized waveforms and circuitry of a prior art boost converter in discontinuous mode operation showing the effect of inductor current overshoot. FIG. 8 shows a simplified prior art synchronous boost topology and the idealized waveforms associated with it. At position “A” on the waveforms, the inductor current crosses through zero. This is the ideal position to turn off the rectifying PMOS transistor, but due to comparator delays and/or offsets, the PMOS does not actually turn off until position “B”. Current is flowing from LX to Vin through the inductor so when the PMOS does turn off the voltage at LX falls below zero and is clamped by the body diode of the NMOS device at position “C”.
FIG. 9 shows an exemplary prior art FET drive circuit with a comparator to turn off the commutating switch. In particular, FIG. 9 illustrates the drive section and power transistors for a typical prior art boost converter using idealized electronic components. A switch S1 represents the NMOS power switch and a switch S2 represents the PMOS switch used for rectification. A comparator X1 senses the polarity of the voltage across switch S2 and turns off switch S2 when the polarity indicates that current is flowing from Vout into LX. A DFF (D type flip flop) U2 ensures that once switch S2 has been turned off it cannot be turned on again until the next clock cycle. Inverters U3, U4, U5, U6, U7, and U8 mimic what would be seen in an actual transistor representation of the drive circuitry. A NOR gate U9 and a NAND gate U1 ensure that switch S1 and switch S2 are never on at the same time so that large currents do not flow directly from VOUT to VGND.
FIG. 10 shows exemplary simulation results for the prior art synchronous boost controller shown in FIG. 9 when it is used in a boost configuration. Due to finite delay times of the comparator and associated circuitry, the inductor current actually goes negative for part of each cycle. The voltage at LX is also negative when the inductor current is negative. These negative voltages and currents adversely impact the performance of the boost converter and their removal is an aspect of the present invention in accordance with an ideal diode approximation embodiment thereof.
Comparator offset voltages will cause the perfect diode to turn off before or after the current has actually dropped to zero; both cases leave unwanted energy in the inductor when both switches are off. To meet continuously more stringent performance specifications, switching regulator designers are forced to increase the speed of their perfect diode comparators, which, unfortunately, wastes more power. They are also forced to design low offset comparators, which may increase the area required for the circuitry as well as slow down the response time of the comparator, thereby negatively impacting overall regulator performance. If the designers constructs the comparator with a fixed offset that compensates for the delay of the comparator, the designer is faced with a dilemma that normal manufacturing process variations will result in unacceptable yield losses at least due to the fact that the fixed offset will only improve the performance in some of the regulators, while some other units will have too much offset and still some others will have too little.
In view of the foregoing, there is a need for a more efficient synchronous switch for switching regulators that tends to not negatively impact performance or production yield. It would also be desirable if the synchronous switch is able to minimize the overshoot current.
Unless otherwise indicated illustrations in the figures are not necessarily drawn to scale.